Solid state memory (ssm), computer system including an ssm, and method of operating an ssm

ABSTRACT

In one aspect, data is stored in a solid state memory which includes first and second memory layers. A first assessment is executed to determine whether received data is hot data or cold data. Received data which is assessed as hot data during the first assessment is stored in the first memory layer, and received data which is first assessed as cold data during the first assessment is stored in the second memory layer. Further, a second assessment is executed to determine whether the data stored in the first memory layer is hot data or cold data. Data which is then assessed as cold data during the second assessment is migrated from the first memory layer to the second memory layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a divisional of application Ser. No. 13/647,630, filed Oct. 9,2013, which is a divisional of Ser. No. 13/027,299, filed Feb. 15, 2011,which is a divisional of application Ser. No. 12/015,548, filed Jan. 17,2008, which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to memory systems, and moreparticularly, the present invention relates to a solid state memory(SSM), a computer system which includes an SSM, and a method ofoperating an SSM. Examples of the SSM include the main memory of acomputer system and the solid state drive (SSD) of a computer system.

A claim of priority is made to Korean Patent Application No.2007-0081832, filed Aug. 8, 2007, the entirety of which is incorporatedherein by reference.

2. Description of the Related Art

A solid state drive (SSD) is a data storage device that typicallyemulates a conventional hard disk drive (HDD), thus easily replacing theHDD in most applications. In contrast to the rotating disk medium of anHDD, an SSD utilizes solid state memory to store data. With no movingparts, an SSD largely eliminates seek time, latency and otherelectro-mechanical delays and failures associated with a conventionalHDD.

An SSD is commonly composed of either NAND flash (non-volatile) or SDRAM(volatile).

SSDs based on volatile memory such as SDRAM are characterized by fastdata access and are used primarily to accelerate applications that wouldotherwise be held back by the latency of disk drives. The volatilememory of the DRAM-based SSDs typically requires the inclusion of aninternal battery and a backup disk system to ensure data persistence. Ifpower is lost, the battery maintains power for sufficient duration ofcopy data from the SDRAM to the backup disk system. Upon restoration ofpower, data is copied back from the backup disk to SDRAM, at which timethe SSD resumes normal operations.

However, most SSD manufacturers use non-volatile flash memory to createmore rugged and compact alternatives to DRAM-based SSDs. These flashmemory-based SSDs, also known as flash drives, do not require batteries,allowing makers to more easily replicate standard hard disk drives. Inaddition, non-volatile flash SSDs retain memory during power loss.

As is well know in the art, single-level cell (SLC) flash is capable ofstoring one bit per memory cell, while multi-level cell (MLC) flash iscapable of storing two or more bits per memory cell. As such, in orderto increase capacity, flash SSDs may utilize multi-level cell (MLC)memory banks. However, flash SSDs generally suffer from relatively slowrandom write speeds, and this operational drawback is furtherexasperated with relatively slow speeds of MLC flash. As such, it hasbeen suggested to equip SSDs with two types of flash storage media—lowercapacity SLC memory banks and higher capacity MLC memory banks. Withsuch a configuration, frequently used data (e.g., directory and/or loginformation) can be stored in the faster SLC banks, while lessfrequently used data (e.g., music files, images, etc.) can be stored inthe slower MLC banks.

SUMMARY OF THE INVENTION

According to an aspect of the present invention, data is stored in asolid state memory which includes first and second memory layers. Afirst assessment is executed to determine whether received data is hotdata or cold data. Received data which is assessed as hot data duringthe first assessment is stored in the first memory layer, and receiveddata which is assessed as cold data during the first assessment isstored in the second memory layer. Further, a second assessment isexecuted to determine whether the data stored in the first memory layeris hot data or cold data. Data which is then assessed as cold dataduring the second assessment is migrated from the first memory layer tothe second memory layer.

According to another aspect of the present invention, a method ofstoring received data in a solid state memory includes initially storinghot data in a high-speed memory layer and, and then migrating a portionof the data stored in the high-speed memory layer to a low-speed memorylayer for storing cold data.

According to yet another aspect of the present invention, a solid statememory system includes a first memory layer, a second memory layer, anda memory controller. The memory controller is configured to execute afirst assessment of whether received data is hot data or cold data, tostore received data which is assessed as hot data during the firstassessment in the first memory layer, and to store received data whichis assessed as cold data during the first assessment in the secondmemory layer. The memory controller is further configured to execute asecond assessment of whether the data stored in the first memory layeris hot data or cold data, and to migrate data which is assessed as colddata during the second assessment from the first memory layer to thesecond memory layer.

According to still another aspect of the present invention, a solidstate memory system is configured to operatively connect to a computeroperating system and comprises first and second memory layers. Anoperational speed of the first memory layer is greater than anoperational speed of the second memory layer, and the first memory areais operationally hidden from the computer operating system when thesolid state memory is operatively connected to the computer operatingsystem.

According to another aspect of the present invention, a computer systemincludes a processor and a memory. The solid state memory includes ahigh-speed memory layer and a low-speed memory layer, and the high-speedmemory area is operationally hidden from the processor.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects and features of the present invention willbecome readily apparent from the detailed description that follows, withreference to the accompanying drawings, in which:

FIG. 1 is a block diagram of a solid state drive (SSD) according to anembodiment of the present invention;

FIGS. 2 and 3 are block diagrams for describing a non-volatile storagemedia in the SSD of FIG. 1 according to an embodiment of the presentinvention;

FIGS. 4 and 5 are block diagrams for describing alternative ways ofcoupling a non-volatile storage media to an interface in the SSD of FIG.1 according to embodiments of the present invention;

FIGS. 6 through 8 are flow charts for use in describing methods ofallocating data to regions of a non-volatile storage media in the SSD ofFIG. 1 according to embodiments of the present invention;

FIG. 9 is a block diagram of the computer system including an SSDaccording to an embodiment of the present invention; and

FIGS. 10 and 11 are block diagrams of a main memory according toembodiments of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention will now be described by way of preferred, butnon-limiting, embodiments of the invention. It is emphasized here thatthe invention is not limited by the exemplary embodiments describedbelow, and that instead the scope of the invention is delimited by theappended claims.

FIG. 1 illustrates a block diagram of a solid state drive (SSD) 1000according to an embodiment of the present invention. As shown, the SSD1000 of this example includes an SSD controller 1200 and non-volatilestorage media 1400.

The SSD controller 1200 includes first and second interfaces 1210 and1230, a controller 1220, and a memory 1240.

The first interface 1210 functions as a data I/O interface with a hostdevice, such as a host central processing unit (CPU) (not shown).Non-limiting examples of the first interface 1210 include UniversalSerial Bus (USB) interfaces, Advanced Technology Attachment (ATA)interfaces, Serial ATA (SATA) interfaces, Small Computer SystemInterface (SCSI) interfaces.

The second interface 1230 functions as a data I/O interface with thenon-volatile storage media 1400. In particular, the second interface1230 is utilized to transmit/receive various commands, addresses anddata to/from the non-volatile storage media 1400. As will be apparent tothose skilled in the art, a variety of different structures andconfigurations of the second interface 1230 are possible, and thus adetailed description thereof is omitted here for brevity.

The controller 1220 and memory 1240 are operatively connected betweenthe first and second interfaces 1210 and 1230, and together function tocontrol/manage the flow of data between the host device (not shown) andthe non-volatile storage media 1400. The memory 1240 may, for example,be an DRAM type of memory device, and the controller 1220 may, forexample, include a central processing unit (CPU), a direct memory access(DMA) controller, and an error correction control (ECC) engine. Examplesof controller functionality may be found in commonly assigned U.S.Patent Publication 2006-0152981, which is incorporated herein byreference. The operations generally executed by controller 1220 (andmemory 1240) to transfer data between the host device (not shown) andSSD memory banks are understood by those skilled in the art, and thus adetailed description thereof is omitted here for brevity. Rather, theoperational description presented later herein is primarily focused oninventive aspects relating to various embodiments of the invention.

Still referring to FIG. 1, the non-volatile storage media 1400 of thisexample includes a high-speed non-volatile memory (NVM) 1410 and alow-speed non-volatile memory (NVM) 1420. As the names suggest, thehigh-speed NVM 1410 is capable of operating at a relatively higher speed(e.g., random write speed) when compared to the low-speed NVM 1420.

In an exemplary embodiment, the high-speed NVM 1410 is single-level cell(SLC) flash memory, and the low-speed NVM 1420 is multi-level cell (MLC)flash memory. However, the invention is not limited in this respect. Forexample, the high-speed NVM 1410 may instead be comprised ofphase-change random access memory (PRAM), or MLC flash memory in whichone bit per cell is utilized. Also, the high-speed NVM 1410 and thelow-speed NVM 1420 may be comprised of the same type of memory (e.g.,SLC or MLC or PRAM), where the operational speed is differentiated byfine-grain mapping in the high-speed NVM 1410 and coarse-grain mappingin the low-speed NVM 1420.

Generally, the high-speed NVM 1410 is utilized to store frequentlyaccessed (written) data such as meta data, and the low-speed NVM 1420 isutilized to store less frequently accessed (written) data such as mediadata. In other words, as will discussed later herein, a write frequencyof data in the high-speed NVM 1410 is statistically higher than a writefrequency of data in the low-speed NVM 1420. Also, due to the nature ofthe respective data being stored, the storage capacity of the low-speedNVM 1420 will typically be much higher than that of the high-speed NVM1410.

In an exemplary embodiment, the high-speed NVM 1410 is hidden from anexternal operating system connected to the SSD. This aspect of theembodiment is illustrated in FIGS. 2 and 3.

Referring collectively to FIGS. 2 and 3, the high-speed NVM 1410 of theexample of this embodiment is a hidden region—that is, the high-speedNVM 1410 is cannot be seen (directly addressed) by the externaloperating system (OS). Rather, the address space shown relative to theOS view is only the low-speed NVM 1420. On the other hand, the addressspace shown relative to the Flash Translation Layer (FTL) is both thehigh-speed NVM 1410 and the low-speed NVM 1420. The FTL translates anaddress provided by the OS into a physical address of the non-volatilestorage media 1400 (i.e., a physical address within the high-speed NVM1410 or the low-speed NVM 1420).

Turning to the block diagrams of FIGS. 4 and 5, there are a number ofdifferent ways in which the high-speed NVM 1410 and the low-speed NVM1420 can be operative connected to the controller 1220 (FIG. 1) via theinterface 1230. In the example of FIG. 4, the high-speed NVM 1410 andthe low-speed NVM 1420 communicate via the interface 1230 using commoninterface channels. In the example of FIG. 5, the high-speed NVM 1410and the low-speed NVM 1420 communicate via the interface 1230 usingseparate interface channels.

It is again noted, however, that the high-speed NVM 1410 and thelow-speed NVM 1420 need not be composed of different types of memory.That is, a single type of memory may be operationally segregated into ahigh-speed layer and a low-speed layer. For example, the grain mappingin the two layers may differ, or the number of bits utilized per cell inthe two layers may differ. Further, the high-speed memory layer and thelow-speed memory layer may be segregated at the chip level (e.g.,contained in different memory chips), or within the same memory chip(e.g., contained in different memory blocks or groups of memory cells ofthe same memory chip).

An operational description of the SSD according to embodiments of thepresent invention is presented next.

According to an embodiment of the present invention in which data isstored in the SSD, a first assessment is executed to determine whetherreceived data is hot data or cold data. As will be understood by thoseskilled in the art, “hot” data is a term of art that refers to datawhich is frequently written or updated (requiring write access), such adirectory information and/or logging information. “Cold” data is allother data, i.e., data which is not frequently written or updated, suchas image files, sound files, program code and so on. Cold data may bewritten once or infrequently, but read frequently. Thus, it is thefrequency of write access that separates hot data from cold.

Received data which is assessed as hot data during the first assessmentis stored in the high-speed NVM 1410, and received data which is firstassessed as cold data during the first assessment is stored in thelow-speed NVM 1420.

Then, a second assessment is executed to determine whether the datastored in the high-speed NVM 1410 is hot data or cold data. In otherwords, the data stored in the high-speed NVM 1410 reassessed todetermine with the data should be reclassified as cold data. Data whichis then assessed as cold data during the second assessment is migratedfrom the high-speed NVM 1410 to the low-speed NVM 1420.

By periodically migrating data which initially determined to be hot datafrom the high-speed NVM 1410 to the low-speed NVM 1420, the size of thehigh-speed NVM 1410 can be reduced. This can potentially result in costsavings, and increase the overall storage capacity of the SSD (e.g., byallowing for more space for the high-capacity MLC layer).

The second assessment and migration of data to the low-speed NVM 1420can be programmed to occur, for example, when the unused capacity of thehigh-speed NVM 1410 is less than a preset value. Alternately, forexample, the second assessment and migration of data to the low-speedNVM 1420 can be programmed to occur at given periodic intervals, or whenthe SSD is idle. Examples of an idle state may include periods in whichno read/write request is received from the host, or when the activationratio or intensity of read/write requests is less than a threshold.

FIG. 6 is a flow chart for use in describing the first assessment andstorage (write) of data in the SSD according to an embodiment of thepresent invention.

Initially, at step 100, a write command, an address and data arereceived. Then, at step 110, a determination is made as to whether thereceived data is classified as hot data. If the received data isclassified as hot data, the received data is stored in the high-speedNVM 1410 at step 120. On the other hand, if the received data is notclassified as hot data, the received data is stored in the low-speed NVM1420 at step 130.

It should be noted that data stored in the low-speed NVM 1420 at step130 may first be “passed through” the high-speed NVM 1410. In otherwords, the data may first be briefly (temporarily) stored in thehigh-speed NVM 1410, and then stored in the low-speed NVM. In this case,the high-speed NVM 1410 essentially acts as a memory buffer for thelow-speed NVM 1420.

FIG. 7 is a flow chart for use in describing the first assessment andstorage (write) of data in the SSD according to another embodiment ofthe present invention.

Initially, at step 300, a write command, an address and data arereceived. Then, at steps 310 a through 310 e, a determination is made asto whether the received data is to be classified as hot data. If thereceived data is classified as hot data, and if there is sufficientavailable space in the high-speed NVM 1410 (step 320), the received datais stored in the high-speed NVM 1410 at step 340. On the other hand, ifthe received data is not to be classified as hot data, or if there isinsufficient available space in the high-speed NVM 1410, the receiveddata is stored in the low-speed NVM 1420 at step 330.

There are a number of different ways in which the received data might beclassified as hot data, and steps 310 a through 310 e of FIG. 7represent a non-exhaustive list of decision processes which can be usedin the classification. These steps can be used in combinations of two ormore, or individually, depending on the desired level of accuracy in thefirst assessment of the received data.

At step 310 a, a determination is made as to whether the operatingsystem (OS) has provided information that the data is hot data. If so,the data is classified as hot data, and the process proceeds to step320.

At step 310 b, a determination is made as to whether the write count ofthe logical block address has exceeded a predetermined threshold. If so,the data is classified as hot data, and the process proceeds to step320.

At step 310 c, a determination is made as to whether the request size ofthe data is less then predetermined threshold (e.g., less than 32 KB).If so, the data is classified as hot data, and the process proceeds tostep 320.

At step 310 d, a determination is made as to whether there is anon-sequential address increment relative to the previously receivedcommand. If so, the data is classified as hot data, and the processproceeds to step 320.

At step 310 e, a determination is made as to whether a merge operationis likely to be induced in the low-speed NVM. If so, the data isclassified as hot data, and the process proceeds to step 320.

Although not shown in FIG. 7, in the case where insufficient spaceexists in the high-speed NVM (step 320), and alternative would be tocreate available space by migrating already stored cold data of thehigh-speed NVM to the low-speed NVM, and then storing the new hot datain the high-speed NVM.

Also, with reference to above-described processes of FIGS. 6 and 7, itis noted that the embodiments thereof are not limited to storing all ofthe hot and cold data in the high-speed and low-speed NVMs,respectively. For example, some of the data initially assessed as colddata may be stored in the high-speed NVM. Also, though less preferable,some of the data initially assessed as hot data may be stored in thelow-speed NVM.

FIG. 8 is a flow chart for use in describing an example of the secondassessment and migration of data to the low-speed NVM in the SSDaccording to an embodiment of the present invention.

Initially, at step 410, a determination is made as to whether an unusedmemory capacity of the high-speed NVM is less than a predeterminedthreshold value. As suggested previously, this step can be supplementedwith (or replaced with) a periodic execution step in which step 410 (orstep 420 below) is executed at periodic intervals, and/or with a SSDidle determination step in which step 410 (or step 420) is executed atperiodic intervals.

Next, at step 420, a determination is made as to whether data stored inthe high-speed NVM is hot data, i.e., whether the data may bereclassified as cold data.

Then, at step 430, reclassified cold data which stored in the high-speedNVM is migrated to the low-speed NVM.

There are a number of different ways in which the determination of step420 may be executed. For example, it is possible to examine the writecount value of each valid data in the high-speed NVM, and to thenreclassify data having low write counts as cold data. Alternately, it ispossible to carry out a FIFO-type assessment in which old (first come)valid data is reclassified as cold data.

With reference to above-described process of FIG. 8, it is noted thatthe embodiment thereof is not limited to migrating all of the cold datato the low-speed NVM. For example, some of the data assessed as colddata may be retained in the high-speed NVM.

FIG. 9 is a block diagram of a computer system according to anembodiment of the present invention. As shown in the figure, a processor(host) 2100 and main memory 2200 communicate over a data bus 2001. Alsoconnected to the bus 2001 are an output device 2500 (e.g., display), aninput device 2300 (e.g., keyboard), other I/O devices 2400, and a solidstate drive SSD. The solid state drive is configured according to one ormore of the previously described embodiments of the invention.

Embodiments of the present invention have been described primarily inthe context of solid state drives (SSDs). However, the invention is notlimited to SSD applications. For example, FIG. 10 illustrates anembodiment where the high-speed memory layer and the low speed memorylayer constitute the main memory 2200 of the computer system shown inFIG. 9. In FIG. 10, the high-speed memory layer 1510 includes DRAM cellsand may be a hidden region relative to the processor 2100 of FIG. 9. Thelow-speed memory layer 1520 of FIG. 10 includes flash cells (either SLCor MLC) and may be open relative to the processor 2100 of FIG. 9. FIG.11 illustrates another example of a main memory 2200. As shown, thehigh-speed memory layer 1610 includes DRAM cells and may be a hiddenregion relative to the processor 2100 of FIG. 9, and the low-speedmemory layer 1620 includes phase-change random access memory (PRAM)cells and may be open relative to the processor 2100 of FIG. 9.

The above-disclosed subject matter is to be considered illustrative, andnot restrictive, and the appended claims are intended to cover all suchmodifications, enhancements, and other embodiments, which fall withinthe true spirit and scope of the present invention. Thus, to the maximumextent allowed by law, the scope of the present invention is to bedetermined by the broadest permissible interpretation of the followingclaims and their equivalents, and shall not be restricted or limited bythe foregoing detailed description.

1-26. (canceled)
 27. A solid state device comprising: a first memory; asecond memory, the first memory being capable of operating at a higherspeed than the second memory; and a control unit configured to determinewhether an available area of the first memory is less than apredetermined value, the control unit being configured to determinewhether data stored in the first memory is a first-type data or asecond-type data, the control unit being configured to move the datastored in the first memory to the second memory based on thedetermination whether the available area of the first memory is lessthan the predetermined value and on the determination whether the datastored in the first memory is the first-type data or the second-typedata.
 28. The solid state device of claim 27, wherein, if the datastored in the first memory is determined as the second-type data, thedata that is stored in the first memory and is determined as the seconddata is moved to the second memory.
 29. The solid state device of claim27, wherein, if the available area of the first memory is less than thepredetermined value, the data stored in the first memory is moved to thesecond memory.
 30. The solid state device of claim 27, wherein thecontrol unit is configured to determine whether a write count of thedata stored in the first memory is equal to or greater than apredetermined count value.
 31. The solid state device of claim 30,wherein the data stored in the first memory is determined to be thefirst-type data if the write count of the data is equal to or greaterthan the predetermined count value, and the data is determined to be thesecond-type data if the write count of the data is less than thepredetermined count value.
 32. The solid state device of claim 27,wherein the control unit is configured to determine whether a size ofthe data is less than a predetermined size value before the data isinitially stored in the first memory or in the second memory.
 33. Thesolid state device of claim 32, the data is initially stored in thefirst memory if the size of the data is less than the predetermined sizevalue, and the data is initially stored in the second memory if the sizeof the data is equal to or greater than the predetermined size value.34. The solid state device of claim 33, wherein the predetermined sizevalue is 32 KB.
 35. The solid state device of claim 27, wherein both thefirst memory and the second memory include multi-level memory cells, thenumber of bit per cell in the second memory being greater than thenumber of bit per cell in the first memory.
 36. The solid state deviceof claim 27, wherein the first memory includes single-level memorycells, and the second memory includes multi-level memory cells.
 37. Thesolid state device of claim 36, wherein the first memory is asingle-level cell flash memory, and the second memory is a multi-levelcell flash memory.
 38. The solid state device of claim 27, wherein thecontrol unit determines whether the data stored in the first memory isthe first-type data or the second-type data only if the available areaof the first memory is less than the predetermined capacity value. 39.The solid state device of claim 27, wherein a storage capacity of thesecond memory is higher than a storage capacity of the first memory. 40.A method of storing data to a non-volatile memory device including afirst memory and a second memory, the first memory being capable ofoperating at a higher speed than the second memory, comprising:determining by a control unit whether the data stored in the firstmemory is a first-type data or a second-type data; determining whetheran available area of the first memory is less than a predeterminedvalue; and moving the data from the first memory to the second memorybased the determination whether the available area of the first memoryis less than the predetermined value and on the determination whetherthe data stored in the first memory is the first-type data or thesecond-type data.
 41. The method of claim 40, wherein the moving thedata from the first memory to the second memory is performed if theavailable area of the first memory is less than the predetermined value.42. The method of claim 40, wherein the moving the data from the firstmemory to the second memory if the data is determined as the second-typedata.
 43. The method of claim 40 further comprising: determining whethera size of the data is less than a predetermined size value before thedata is initially stored in the first memory or in the second memory;and initially storing the data in the first memory if the size of thedata is less than the predetermined size value, and storing the date inthe second memory if the size of the data is equal to or greater thanthe predetermined size value.
 44. A solid state device comprising: afirst memory; a second memory, the first memory being capable ofoperating at a higher speed than the second memory; and a control unitconfigured to determine whether a size of received data is less than apredetermined size value, the control unit being configured to determinewhether an available area of the first memory is less than apredetermined area value, the control unit being configured to determinewhether a write count of data stored in the first memory is equal to orgreater than a predetermined count value, wherein the received data isinitially stored in the first memory if the size of the received data isless than the predetermined size value, and the received data isinitially stored in the second memory if the size of the received datais equal to or greater than the predetermined size value, and whetherthe data stored in the first memory is moved to the second memory if theavailable area of the first memory is less than the predetermined areavalue and the write count of data stored in the first memory is equal toor greater than the predetermined count value.
 45. The solid statedevice of claim 44, wherein the control unit determines whether thewrite count of the data stored in the first memory is equal to orgreater than the predetermined count value when the available area ofthe first memory is less than the predetermined area value.
 46. Thesolid state device of claim 44, wherein the control unit determineswhether the write count of the data stored in the first memory is equalto or greater than the predetermined count value, when no read or writerequest is received.